Background and Objectives: The transition of digital technology from a binary base to a ternary number system, that is, the use of three possible states within one digit – false/uncertain/true – allows one to obtain a number of advantages and, in general, provides a real opportunity to increase the performance of microprocessor technology, all other things being equal. The presence of functional analog models of basic and additional combinational ternary logical elements in CAD systems allows the correct modeling of complex devices of digital ternary technology. So, the goal of the work is to develop the main combinational units of the ternary processor, which are main parts of its arithmetic logic unit. Materials and Methods: The software package for analysis and automatic design of electronic circuits was used to develop analog models of ternary logic elements. This program made it possible to analyze transient processes, parameters and interaction features of the developed logical elements and ternary digit units, based on such elements. Results: Based on analog models of basic and additional ternary logic elements, a controlled inverter, a single-bit ternary adder modulo 3, half-carry and full-carry circuits, a ternary half adder and a full ternary single-bit adder have been designed. Conclusion: The developed nodes, along with the previously presented basic ternary combinational logical elements, have allowed to further implement on their basis the heart of the ternary processor – the arithmetic logic unit.